Insider Brief
- Signaloid has completed the tapeout of its C0-ASIC AI accelerator, a chip designed for energy-efficient robotics and physical AI workloads, with engineering samples expected to ship to its first customer in the third quarter of 2026.
- The company said the chip uses its distribution-extended computing architecture to reduce the energy required for AI workloads involving uncertainty, probability and randomized calculations compared with conventional CPU- and GPU-based approaches.
- The UK Advanced Research and Invention Agency (ARIA) plans to evaluate systems based on the C0-ASIC for next-generation AI techniques, including second-order methods, while Signaloid developed the chip with IC-Link, Cadence Design Systems and manufacturing partner TSMC.
Signaloid announced it has completed the tapeout of a new AI accelerator chip designed for energy-efficient robotics and physical AI workloads, with engineering samples expected to reach its first customer in the third quarter of 2026.
The chip, known as the C0-ASIC, is based on its distribution-extended computing architecture, which uses mathematical techniques to restructure certain computations rather than relying on the brute-force processing approach commonly used by CPUs and GPUs. That approach can significantly reduce the energy required for workloads involving uncertainty, probability and randomized calculations, according to Signaloid.
The UK Advanced Research and Invention Agency (ARIA) will deploy systems based on the chip to evaluate next-generation AI techniques, including second-order methods, which aim to improve the efficiency of AI training and optimization.
“The Scaling Compute program at ARIA commissioned several innovative technology prototypes pursuing unconventional ideas to design new AI accelerators,” noted Suraj Bramhavar, ARIA program director. “We commissioned Signaloid’s C0-ASIC for evaluation in randomized numerical linear algebra and probabilistic computing workloads. We believe randomized linear algebra represents a fundamentally new and powerful technique underpinning many applications in computer science including AI, and exploiting these principles in hardware could provide an entirely new vector for improved performance. We are excited to invest behind this theme, in partnership with Signaloid, to explore its full potential.”
The C0-ASIC was developed in collaboration with semiconductor design partners IC-Link, part of imec, and Cadence Design Systems, with manufacturing through Taiwan Semiconductor Manufacturing Co. Additional FPGA-based systems implementing the same architecture are also under discussion for deployment in the United Kingdom and Switzerland later this year.
Founded by former University of Cambridge professor Phillip Stanley-Marbell, Signaloid develops computing hardware and software for applications that process probability distributions and uncertainty. The company said its technology is currently used by more than 3,000 customers and researchers through cloud, on-premises and edge-computing deployments.
